AML-S905X-CC-V2 / L1 & L2 CPU-Cache size

Hardware
1

Hi there,

did anyone had a the info about the L1 and L2 cpucache size?

localhost ~ # lstopo-no-graphics
Machine (1947MB total)
  Package L#0
    NUMANode L#0 (P#0 1947MB)
    L2 L#0 (0KB)
      L1d L#0 (0KB) + L1i L#0 (0KB) + Core L#0 + PU L#0 (P#0)
      L1d L#1 (0KB) + L1i L#1 (0KB) + Core L#1 + PU L#1 (P#1)
      L1d L#2 (0KB) + L1i L#2 (0KB) + Core L#2 + PU L#2 (P#2)
      L1d L#3 (0KB) + L1i L#3 (0KB) + Core L#3 + PU L#3 (P#3)

Architektur:                       aarch64
  CPU Operationsmodus:             32-bit, 64-bit
  Byte-Reihenfolge:                Little Endian
CPU(s):                            4
  Liste der Online-CPU(s):         0-3
Anbieterkennung:                   ARM
  BIOS-Anbieterkennung:            ARM Limited
  Modellname:                      Cortex-A53
    BIOS-Modellname:                 CPU @ 0.0GHz
    BIOS-Prozessorfamilie:         2
    Modell:                        4
    Thread(s) pro Kern:            1
    Kern(e) pro Cluster:           4
    Sockel:                        1
    Cluster:                       1
    Stepping:                      r0p4
    Skalierung der CPU(s):         100%
    Maximale Taktfrequenz der CPU: 1416,0000
    Minimale Taktfrequenz der CPU: 100,0000
    BogoMIPS:                      48,00
    Markierungen:                  fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid

 getconf -a | grep CACHE
LEVEL1_ICACHE_SIZE                 0
LEVEL1_ICACHE_ASSOC                0
LEVEL1_ICACHE_LINESIZE             64
LEVEL1_DCACHE_SIZE                 0
LEVEL1_DCACHE_ASSOC                0
LEVEL1_DCACHE_LINESIZE             64
LEVEL2_CACHE_SIZE                  0
LEVEL2_CACHE_ASSOC                 0
LEVEL2_CACHE_LINESIZE              0
LEVEL3_CACHE_SIZE                  0
LEVEL3_CACHE_ASSOC                 0
LEVEL3_CACHE_LINESIZE              0
LEVEL4_CACHE_SIZE                  0
LEVEL4_CACHE_ASSOC                 0
LEVEL4_CACHE_LINESIZE              0

I don’t get it :frowning:

2

This is set in the device tree that gets passed from u-boot to Linux. As the u-boot DT is slightly older and the caches were only added to Linux recently, it will be a few months before this information is added to the u-boot device tree. We willl do it for the onboard u-boot in our annual update cycle for non-critical firmware fixes.

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