Rockchip RK3328’s BootROM will enter device mode if it is unable to find a relevant bootloader on external media. In this mode, the SoC accept commands using a custom Rockchip protocol.
The two main VCRs (Vendor Control Requests) are:
- 0x0471 Transfer to SRAM
- 0x0472 Transfer to DRAM
When the SoC is powered on, it does not have access to the DRAM so there is only a tiny bit of memory available. It searches for code on storage devices. Once it finds the code it’s looking for, provided that it exists, the SoC will load it into SRAM and run it. Under normal circumstances, this code will initialize DRAM specific to that board’s configuration.
VCR 0x0471 is the USB command equivalent of that. The initialization code is copied over USB to the SoC SRAM, runs to bring up DRAM, and then goes back to BootROM.
Now that DRAM is up, the board would load the secondary loaders. This is well documented by Jonas Karlman.
CONFIG_LNX_KRNL_IMG_TEXT_OFFSET_BASE=0x00200000
CONFIG_TEXT_BASE=0x00200000
CONFIG_SYS_MALLOC_LEN=0x8000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
CONFIG_SF_DEFAULT_MODE=0x0
CONFIG_ENV_SIZE=0x1000
CONFIG_SPL_TEXT_BASE=0x0
CONFIG_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x8000
CONFIG_ROCKCHIP_BOOT_MODE_REG=0xff1005c8
CONFIG_ROCKCHIP_STIMER_BASE=0xff1d0020
CONFIG_TPL_TEXT_BASE=0xff091000
CONFIG_TPL_STACK=0xff098000
CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_SPL_STACK=0x400000
CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
CONFIG_ERR_PTR_OFFSET=0x0
CONFIG_SPL_SIZE_LIMIT=0x0
CONFIG_DEBUG_UART_BASE=0xFF130000
CONFIG_IMX_DCD_ADDR=0x00910000
CONFIG_SYS_MEM_TOP_HIDE=0x0
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_TPL_MAX_SIZE=0x7000
CONFIG_TPL_SIZE_LIMIT=0x0
CONFIG_SYS_MEMTEST_START=0x800800
CONFIG_SYS_MEMTEST_END=0x7fffffff
CONFIG_STACK_SIZE=0x1000000
CONFIG_SYS_SRAM_BASE=0x0
CONFIG_SYS_SRAM_SIZE=0x0
CONFIG_FIT_EXTERNAL_OFFSET=0x0
CONFIG_SPL_LOAD_FIT_ADDRESS=0x0
CONFIG_BOOTSTAGE_STASH_SIZE=0x1000
CONFIG_SPL_MAX_SIZE=0x20000
CONFIG_SPL_PAD_TO=0x20000
CONFIG_SPL_BSS_START_ADDR=0x2000000
CONFIG_SPL_BSS_MAX_SIZE=0x2000
CONFIG_SPL_SYS_STACK_F_CHECK_BYTE=0xaa
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x100000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x140
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET=0x0
CONFIG_SYS_SPI_U_BOOT_OFFS=0x28000
CONFIG_SYS_BOOTM_LEN=0x8000000
CONFIG_BOOTP_PXE_CLIENTARCH=0x16
CONFIG_SPL_DEBUG_UART_BASE=0xFF130000
CONFIG_TPL_DEBUG_UART_BASE=0xFF130000
CONFIG_VIDEO_LOGO_MAX_SIZE=0x100000
CONFIG_IMAGE_SPARSE_FILLBUF_SIZE=0x80000
CONFIG_SYS_FDT_PAD=0x3000
CONFIG_SPL_OF_LIBFDT_ASSUME_MASK=0xff
CONFIG_TPL_OF_LIBFDT_ASSUME_MASK=0xff
CONFIG_TOOLS_FIT_SIGNATURE_MAX_SIZE=0x10000000