tinymembench v0.4.9 (simple benchmark for memory throughput and latency)
==========================================================================
== Memory bandwidth tests ==
== ==
== Note 1: 1MB = 1000000 bytes ==
== Note 2: Results for 'copy' tests show how many bytes can be ==
== copied per second (adding together read and writen ==
== bytes would have provided twice higher numbers) ==
== Note 3: 2-pass copy means that we are using a small temporary buffer ==
== to first fetch data into it, and only then write it to the ==
== destination (source -> L1 cache, L1 cache -> destination) ==
== Note 4: If sample standard deviation exceeds 0.1%, it is shown in ==
== brackets ==
==========================================================================
C copy backwards : 3708.2 MB/s (0.2%)
C copy backwards (32 byte blocks) : 3705.9 MB/s
C copy backwards (64 byte blocks) : 3707.0 MB/s
C copy : 3703.3 MB/s
C copy prefetched (32 bytes step) : 3690.8 MB/s
C copy prefetched (64 bytes step) : 3692.1 MB/s
C 2-pass copy : 3398.6 MB/s
C 2-pass copy prefetched (32 bytes step) : 3461.7 MB/s
C 2-pass copy prefetched (64 bytes step) : 3461.1 MB/s
C fill : 8896.3 MB/s (0.7%)
C fill (shuffle within 16 byte blocks) : 8887.8 MB/s
C fill (shuffle within 32 byte blocks) : 8894.8 MB/s
C fill (shuffle within 64 byte blocks) : 8893.5 MB/s
---
standard memcpy : 3688.0 MB/s
standard memset : 8895.5 MB/s (0.6%)
---
NEON LDP/STP copy : 3703.8 MB/s
NEON LDP/STP copy pldl2strm (32 bytes step) : 3701.2 MB/s
NEON LDP/STP copy pldl2strm (64 bytes step) : 3701.1 MB/s
NEON LDP/STP copy pldl1keep (32 bytes step) : 3691.2 MB/s
NEON LDP/STP copy pldl1keep (64 bytes step) : 3688.8 MB/s
NEON LD1/ST1 copy : 3702.7 MB/s
NEON STP fill : 8886.7 MB/s (0.6%)
NEON STNP fill : 8877.0 MB/s
ARM LDP/STP copy : 3704.2 MB/s
ARM STP fill : 8879.5 MB/s (0.5%)
ARM STNP fill : 8854.3 MB/s
==========================================================================
== Memory latency test ==
== ==
== Average time is measured for random memory accesses in the buffers ==
== of different sizes. The larger is the buffer, the more significant ==
== are relative contributions of TLB, L1/L2 cache misses and SDRAM ==
== accesses. For extremely large buffer sizes we are expecting to see ==
== page table walk with several requests to SDRAM for almost every ==
== memory access (though 64MiB is not nearly large enough to experience ==
== this effect to its fullest). ==
== ==
== Note 1: All the numbers are representing extra time, which needs to ==
== be added to L1 cache latency. The cycle timings for L1 cache ==
== latency can be usually found in the processor documentation. ==
== Note 2: Dual random read means that we are simultaneously performing ==
== two independent memory accesses at a time. In the case if ==
== the memory subsystem can't handle multiple outstanding ==
== requests, dual random read has the same timings as two ==
== single reads performed one after another. ==
==========================================================================
block size : single random read / dual random read, [MADV_NOHUGEPAGE]
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.0 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.0 ns / 0.0 ns
16384 : 0.0 ns / 0.0 ns
32768 : 0.0 ns / 0.0 ns
65536 : 4.0 ns / 6.4 ns
131072 : 6.1 ns / 8.6 ns
262144 : 8.8 ns / 11.4 ns
524288 : 10.1 ns / 13.1 ns
1048576 : 12.7 ns / 16.4 ns
2097152 : 97.5 ns / 147.7 ns
4194304 : 139.3 ns / 185.9 ns
8388608 : 164.2 ns / 202.8 ns
16777216 : 176.3 ns / 212.4 ns
33554432 : 182.7 ns / 218.2 ns
67108864 : 192.4 ns / 233.1 ns
block size : single random read / dual random read, [MADV_HUGEPAGE]
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.0 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.0 ns / 0.0 ns
16384 : 0.0 ns / 0.0 ns
32768 : 0.0 ns / 0.0 ns
65536 : 4.0 ns / 6.4 ns
131072 : 6.0 ns / 8.6 ns
262144 : 7.1 ns / 9.4 ns
524288 : 7.6 ns / 9.8 ns
1048576 : 9.5 ns / 12.0 ns
2097152 : 94.1 ns / 144.9 ns
4194304 : 134.5 ns / 182.7 ns
8388608 : 153.3 ns / 192.2 ns
16777216 : 162.6 ns / 196.9 ns
33554432 : 167.3 ns / 199.2 ns
67108864 : 172.7 ns / 200.9 ns